SPI flash / SMI/SMM + some observations (AM5)
Posted: 17 Jul 2026, 16:20
hello guys, can we do some testings?
in short: SMI - smi - system management interrupt is type of event when device like thermal / voltage sensors triggers hardware event that forces the cpu to pause its current execution, save its state to smram, and jump to a high-priority firmware handler. this effectively "freezes" the system's time signature—halting the tsc and blocking all other i/o operations until the smm routine completes and returns control back to the os.
smi events: thermal monitoring and management for polling sensors and adjusting power limits, dynamic voltage regulation through vrm communication, power management for handling c-state , system error reporting for logging hardware issues, legacy hardware emulation
smm handler code: it's image stored in uefi firmware inside spi flash , it's accessed by spi flash controller in your pch, the image is copied to your smram which is reserved and hardware protected memory region.
SMI event itself is invisible to OS and is literally stealing your cpu time, if this events were handled and visible to os , it should be easily debugable and scheduled.
What i want you to test is increase spi bus speed:
Switch from auto/disabled to Enable
Setup Question = ESPI Enable
Help String = No help string
Token =116 // Do NOT change this line
Offset =62
Width =01
BIOS Default =[0F]Auto
Options =[00]Disabled // Move "*" to the desired Option
*[01]Enabled
[0F]Auto
Setup Question = HID Enable
Help String = No help string
Token =119 // Do NOT change this line
Offset =AD
Width =01
BIOS Default =[0F]Auto
Options =[00]Disabled // Move "*" to the desired Option
*[01]Enabled
[0F]Auto
Setup Question = HID Spi Read Mode
Help String = No help string
Token =11A // Do NOT change this line
Offset =180
Width =01
BIOS Default =[05]Quad IO 1-4-4
Options =*[05]Quad IO 1-4-4 // Move "*" to the desired Option <--- keep this default
[04]Dual IO 1-2-2
[07]Fast Read 1-1-1
Setup Question = HID Spi Speed
Help String = No help string
Token =11B // Do NOT change this line
Offset =181
Width =01
BIOS Default =[07]spi_spd7
Options =[01]33MHz // Move "*" to the desired Option
[02]22MHz
[03]17.6MHz
[05]800KHz
[06]spi_spd6
*[07]spi_spd7 <--- use highest possible frequency or spd profile
Locate your spi spd profile and change the freq:
Setup Question = HID Spi Speed7 N
Help String = Spi Speed7 = 200Mhz/HID Spi Speed7 N
Token =11D // Do NOT change this line
Offset =183
Width =01
BIOS Default =32 <--- default
Value =4 <---change it lowest possible value u can , most likely to be 4.. 200/4= 50 mhz
Change this to "distributed" !
Setup Question = Location of private memory regions
Help String = Controls whether or not the private memory regions (PSP, SMU and CC6) are at the top of DRAM, at the top of 1st DRAM pair or distributed. Note that distributed requires memory on all dies. Note that it will always be at the top of DRAM if some dies don't have memory regardless of this option's setting.
Token =43 // Do NOT change this line
Offset =1C5
Width =01
BIOS Default =[FF]Auto
Options =*[00]Distributed // Move "*" to the desired Option
[01]Consolidated
[02]Consolidated to 1st DRAM pair
[FF]Auto
What we did: increased bus frequency when spi controller reads vars from uefi
Private regions distributed: SMU buffers are spread evenly across both memory channels instead of concentrated on one. SMM handlers that touch these regions get parallel channel access, reducing SMI handler duration and jitter INCREASING responsiveness
Runs absolutely perfect for me
unrelated to main post /////
observation 1: hid implementation bugs across multiple platforms and motherboard vendors—including z790 gigabyte aorus, z790 asrock nova, and x870 apex—consistently cause high-polling-rate mice like the razer deathadder v3 and endgame op1 to default to incorrect, significantly lower polling rates (250hz, 500hz, or 800hz) upon system boot. this persists despite having the latest firmware installed on both devices, and the only reliable way to force the controller to renegotiate the intended 8000hz connection is a physical replug of the mouse. Each time you start pc , check your polling rate https://cpstest.org/polling-rate-test/
observation 2 : u can play whole day deadmatch and everything just "works enough", then u decide to play some premier or unranked, as you play the warmup it's pretty much same as when you played the deadmatch, u're owning people while waiting another players to connect and when they do and game goes live , mouse sensitivity and mouse responsiveness is instantly worse. Also , in my case there is like 0.25ms hard freeze after warmup timer ends and scene transition goes to team overview scene (scene where you see your teammates and their skins, same that plays after game ends).
observation 3: for users with external usb audio interfaces like the scarlett, enabling the "usb audio controller" setting is mandatory, without it, the system experiences audio dropouts and severe inconsistencies in spray and hit registration, even when dpc latency appears low.
in short: SMI - smi - system management interrupt is type of event when device like thermal / voltage sensors triggers hardware event that forces the cpu to pause its current execution, save its state to smram, and jump to a high-priority firmware handler. this effectively "freezes" the system's time signature—halting the tsc and blocking all other i/o operations until the smm routine completes and returns control back to the os.
smi events: thermal monitoring and management for polling sensors and adjusting power limits, dynamic voltage regulation through vrm communication, power management for handling c-state , system error reporting for logging hardware issues, legacy hardware emulation
smm handler code: it's image stored in uefi firmware inside spi flash , it's accessed by spi flash controller in your pch, the image is copied to your smram which is reserved and hardware protected memory region.
SMI event itself is invisible to OS and is literally stealing your cpu time, if this events were handled and visible to os , it should be easily debugable and scheduled.
What i want you to test is increase spi bus speed:
Switch from auto/disabled to Enable
Setup Question = ESPI Enable
Help String = No help string
Token =116 // Do NOT change this line
Offset =62
Width =01
BIOS Default =[0F]Auto
Options =[00]Disabled // Move "*" to the desired Option
*[01]Enabled
[0F]Auto
Setup Question = HID Enable
Help String = No help string
Token =119 // Do NOT change this line
Offset =AD
Width =01
BIOS Default =[0F]Auto
Options =[00]Disabled // Move "*" to the desired Option
*[01]Enabled
[0F]Auto
Setup Question = HID Spi Read Mode
Help String = No help string
Token =11A // Do NOT change this line
Offset =180
Width =01
BIOS Default =[05]Quad IO 1-4-4
Options =*[05]Quad IO 1-4-4 // Move "*" to the desired Option <--- keep this default
[04]Dual IO 1-2-2
[07]Fast Read 1-1-1
Setup Question = HID Spi Speed
Help String = No help string
Token =11B // Do NOT change this line
Offset =181
Width =01
BIOS Default =[07]spi_spd7
Options =[01]33MHz // Move "*" to the desired Option
[02]22MHz
[03]17.6MHz
[05]800KHz
[06]spi_spd6
*[07]spi_spd7 <--- use highest possible frequency or spd profile
Locate your spi spd profile and change the freq:
Setup Question = HID Spi Speed7 N
Help String = Spi Speed7 = 200Mhz/HID Spi Speed7 N
Token =11D // Do NOT change this line
Offset =183
Width =01
BIOS Default =32 <--- default
Value =4 <---change it lowest possible value u can , most likely to be 4.. 200/4= 50 mhz
Change this to "distributed" !
Setup Question = Location of private memory regions
Help String = Controls whether or not the private memory regions (PSP, SMU and CC6) are at the top of DRAM, at the top of 1st DRAM pair or distributed. Note that distributed requires memory on all dies. Note that it will always be at the top of DRAM if some dies don't have memory regardless of this option's setting.
Token =43 // Do NOT change this line
Offset =1C5
Width =01
BIOS Default =[FF]Auto
Options =*[00]Distributed // Move "*" to the desired Option
[01]Consolidated
[02]Consolidated to 1st DRAM pair
[FF]Auto
What we did: increased bus frequency when spi controller reads vars from uefi
Private regions distributed: SMU buffers are spread evenly across both memory channels instead of concentrated on one. SMM handlers that touch these regions get parallel channel access, reducing SMI handler duration and jitter INCREASING responsiveness
Runs absolutely perfect for me
unrelated to main post /////
observation 1: hid implementation bugs across multiple platforms and motherboard vendors—including z790 gigabyte aorus, z790 asrock nova, and x870 apex—consistently cause high-polling-rate mice like the razer deathadder v3 and endgame op1 to default to incorrect, significantly lower polling rates (250hz, 500hz, or 800hz) upon system boot. this persists despite having the latest firmware installed on both devices, and the only reliable way to force the controller to renegotiate the intended 8000hz connection is a physical replug of the mouse. Each time you start pc , check your polling rate https://cpstest.org/polling-rate-test/
observation 2 : u can play whole day deadmatch and everything just "works enough", then u decide to play some premier or unranked, as you play the warmup it's pretty much same as when you played the deadmatch, u're owning people while waiting another players to connect and when they do and game goes live , mouse sensitivity and mouse responsiveness is instantly worse. Also , in my case there is like 0.25ms hard freeze after warmup timer ends and scene transition goes to team overview scene (scene where you see your teammates and their skins, same that plays after game ends).
observation 3: for users with external usb audio interfaces like the scarlett, enabling the "usb audio controller" setting is mandatory, without it, the system experiences audio dropouts and severe inconsistencies in spray and hit registration, even when dpc latency appears low.