Blur Busters Forums

zabra wrote: ↑

29 Dec 2021, 01:14

My name is Ahmed, on many fourms, people know me as Zabra. I used to work on bios firmware for big companies. There is a lot of settings within the BIOS which are locked down by the big brand companies, And I'm here to reveal the reason you guys all feel D-Sync and input latency. Some settings on Intel based motherboards are locked down that cause the system to desync and cause huge issues, for ex. "FastSpeedPlus SCL Low" is read & write locked. Huge problem. The transmitter half-swing is sub-optimal solution due to how the Bus clock times. Generation 3 RX/TX also can severely distort the signal and affect delivery times of ALL INPUTS!!! De-emphasis is also a broken value within many bioses. The programming of static equalization phases is also not truely static. The clock differential slew rate of the base clock which also is modified by spread spectrum clocking's heuristics it retrieves from the sensors is false. Refresh Watermarks is also another setting in bios that messes with ram latency that can really desync the system. I recommend disabling Disable Per Bank Refresh & SelfRefresh & power down to lower ram latency bottlenecks. But be warned, your computer will not fully turn off when trying to power down. You have to turn off your power supply, then turn it back on, and hit the power button (In conclusion for a full reboot). Additionally, OS tweaks are nothing compared to the power the BIOS Configuration withholds. Before I became a bios engineer, I used to think I had bad EMI issues. Unless you have a dryer motor changing speed ontop of your cpu, EMI wont be much of an issue. I have been measuring many different parts for years and the issue is bios!! Replies & Questions are welcome! Excuse my grammar. Non native

a_c_r_e_a_l wrote: ↑

30 Dec 2021, 15:47

Guys, just buy another motherboard and problem solved. That was easy.

zabra wrote: ↑

29 Dec 2021, 01:14

My name is Ahmed, on many fourms, people know me as Zabra. I used to work on bios firmware for big companies. There is a lot of settings within the BIOS which are locked down by the big brand companies, And I'm here to reveal the reason you guys all feel D-Sync and input latency. Some settings on Intel based motherboards are locked down that cause the system to desync and cause huge issues, for ex. "FastSpeedPlus SCL Low" is read & write locked. Huge problem. The transmitter half-swing is sub-optimal solution due to how the Bus clock times. Generation 3 RX/TX also can severely distort the signal and affect delivery times of ALL INPUTS!!! De-emphasis is also a broken value within many bioses. The programming of static equalization phases is also not truely static. The clock differential slew rate of the base clock which also is modified by spread spectrum clocking's heuristics it retrieves from the sensors is false. Refresh Watermarks is also another setting in bios that messes with ram latency that can really desync the system. I recommend disabling Disable Per Bank Refresh & SelfRefresh & power down to lower ram latency bottlenecks. But be warned, your computer will not fully turn off when trying to power down. You have to turn off your power supply, then turn it back on, and hit the power button (In conclusion for a full reboot). Additionally, OS tweaks are nothing compared to the power the BIOS Configuration withholds. Before I became a bios engineer, I used to think I had bad EMI issues. Unless you have a dryer motor changing speed ontop of your cpu, EMI wont be much of an issue. I have been measuring many different parts for years and the issue is bios!! Replies & Questions are welcome! Excuse my grammar. Non native

zabra wrote: ↑

29 Dec 2021, 01:14

The transmitter half-swing is sub-optimal solution due to how the Bus clock times. Generation 3 RX/TX also can severely distort the signal and affect delivery times of ALL INPUTS!!! De-emphasis is also a broken value within many bioses. The programming of static equalization phases is also not truely static. The clock differential slew rate of the base clock which also is modified by spread spectrum clocking's heuristics it retrieves from the sensors is false.